FPGAs may be used to implement large systems that include million of gates and megabits of embedded memory. Of the tasks required in creating and optimizing a design, synthesizing the design, placement of components on the FPGAs, and routing connection between components on the FPGA utilizing available resources can be the most challenging and time consuming. In order to satisfy timing requirements and system specifications, several iterations are often required to determine how the design should be implemented, where components are to be placed on the target device, and which routing resources to allocate to connect the components. The complexity of large systems often requires the use of EDA tools to create and optimize their design onto physical target devices. Automated synthesis, placement and routing algorithms in EDA tools perform the time consuming task synthesis, placement, and routing of components onto physical devices.
A DCS represents a set of one or more values that are not taken for a signal in the system. The values may not be taken generally or in response to one or more conditions. In the past, information about a signal's DCS could be used in the design of a system on a target device. Typically the information would be used only during an early stage of synthesis where a hardware description language (HDL) of the system is converted to building blocks such as adders, registers, multipliers, and other high level building blocks at a register transfer level (RTL). Furthermore, the information regarding a signal's DCS would only be used at a single instance for optimization and then discarded. Further use of information about a signal's DCS would not be utilized after an initial optimization has taken place.